The present invention relates to a semiconductor device and the method thereof, and more particularly, to a semiconductor device provided with an SRAM memory cell and the method thereof. Conventionally, a static random access memory (SRAM) is utilized as a memory means in various kinds of semiconductor devices. The SRAM is made of a plurality of cells for storing data of "High" and "Low". As such cells, there is a high resistance load type.
FIG. 3 shows the conventional circuit of the SRAM cell of the high resistance load type.
As shown in FIG. 3, in the memory cell, sources of a pair of n-channel field effect transistors (hereinafter referred to as an FETs) N1 and N2 are connected with the ground voltage line, and drains thereof are connected to one end of resistance elements R1 and R2, respectively. The other ends of the resistance elements R1 and R2 are connected with a source voltage line supplied with source voltage Vcc.
Here, a node (a) is connected with a gate of the FET N2 and a node (b) is connected with a gate of the FET N1.
The node (a) and a node (c) on a bit line B are connected with a source or a drain of an FET N3, respectively, and a node (d) on an inverting bit line rB and the node (b) are connected with a source or a drain of an FET N4, respectively.
Gates of the FETs N3 and N4 are connected with the same word line W.
Accordingly, when the word line W changes from Low level to High, the written levels stored at the nodes (a) and (b) are transferred to the bit lines B and rB, respectively.
FIGS. 4A-E show the conventional manufacturing process of such an SRAM cell with the node (a) in FIG. 3 as a center.
As shown in FIG. 4A, at first, a source 303, a drain 304, a gate insulating film 305, and a gate electrode 306 formed on the gate insulating film 305 are formed at a predetermined active area defined by a field oxide film 302 on a substrate 301. The source 303, the drain 304, the gate insulating film 305, and the gate electrode 306 constructs the FET N3. Gate electrode film 307 is formed up to an end of the field oxide film 302, and an interlayer insulating film 308 is formed thereon. Side walls 306a are formed on side surfaces of the gate electrode 306. The gate electrode film 307 is connected with the gate electrode of the fet N2, although not shown in FIG. 3.
As shown in FIG. 4B, a resist pattern 309 with an opening formed by photolithography is formed on the interlayer insulating film 308.
As shown in FIG. 4C, the interlayer insulating film 308 is selectively removed with the resist pattern 309 as a mask to form a shared contact region 310.
Next, after the resist pattern 309 is removed, as shown in FIG. 4D, a polysilicon film 311a is deposited over the entire surface, and, as shown in FIG. 4E, by selectively etching the polysilicon film 311a with a resist pattern 312 as a mask, film is formed into a desired shape. Then, impurities is introduced, for example, ion implantation with a predetermined part of the region of the film shape being masked to form a conductive film 311b. It is to be noted that the impurities are not introduced into the masked region and the masked region remains highly resistant to become the resistance element R1. In fact, the resistance element R1 is introduced impurities less than the impurities implanted by the process to control resistance value thereof. In other words, a part of the conductive film 311b is highly resistant to form the resistance element R1 shown in FIG. 3. Although not shown in FIG. 4E, the conductive film 311b is connected with power source line. The drain 304 and the gate electrode film 307 are connected by the conductive film 311b in the above shared contact region 310 to form the above node (a). Such a semiconductor device is described by U.S. Pat. No. 5,204,279.
However, the conventional structure mentioned in U.S. Pat. No. 5,204,279 has a problem that the shared contact region actually formed is larger than the designed value.
In the conventional structure, the resist pattern 309 for forming the shared contact region 310 is actually formed as a resist pattern 309a having a larger opening, as shown in FIGS. 5A-5B. More specifically, the resist pattern 309a is obtained as a result of partially illuminating a desired region of an applied photoresist by a photolithographic technique to develop the photoresist, and removing the region irradiated by light. In this partial light irradiation, since the end of the gate electrode film 307 is underlying the opening, reflected light 51 from the end of the gate irradiates the back surface of the applied photoresist film. As a result, as shown in FIG. 5A, the resist pattern 309a has an opening larger than the designed value is formed. This phenomenon is more remarkable in the case where a refractory metal silicide is used as a material of the gate electrode line 307.
Next, as described with FIG. 5B, the polysilicon film is deposited over the entire surface, selective etching is performed with a resist pattern 312a as a mask, and impurities are introduced ion implantation into the region other than the region where the resistance is to be formed, to form electrode film 311c. However, since the shared contact region formed is larger than the designed value, the resist pattern 312a formed does not cover the entire shared contact region. As a result, as shown in FIGS. 5C, during the etching for forming the electrode film 311c, a hole is formed even in the substrate 301.
Moroever, when the distance between the gate electrode 306 and the field oxide film 302 is narrower, the opening of the resist 309a is over the gate electrode 306 as shown in FIG. 6A. Thus, in this worst case, a short circuit is caused, as shown in FIG. 6B. Therefore, it is difficult to improve the extent of integration.